This project is researching FAST, a methodology to build very fast, cycleaccurate full system computer simulators and building the first set of such simulators and the first set of tools to help construct those simulators. The methodology relies on a functional model that is a fast, full-system but not cycle-accurate simulator coupled with a timing model that is models the micro-architectural structure and arbitration of a computer system, but not its functionality. The way FAST simulators differ from other simulators partitioned in the same way is that the interface between the functional and timing model is optimized to minimize the need for round-trip communication. The optimized communication enables FAST timing models to be implemented in an FPGA and the functional model in software while still achieving extremely high performance. Our general strategy is to design a methodology and then prototype an example using that methodology to ensure the methodology is sound before committing to it. This strategy ensures that the selected methodology has been tested and provides an early example of the output of that methodology.