This document describes a set of routines for a VME DMA module called the Super-VIOR. The Super-VIOR interface routines, also called the SVI routines, are written in PILS and run under a Valet-plus system. These routines enable a program to set up, execute, and monitor DMA operations. The Super-VIOR Interface Routines are written in PILS, a high level language similar to BASIC and Pascal which is powerful and fast enough for most applications. One of the most powerful features of the Valet/PILS system is the ability to set up exception vectors and exception handlers directly in a program. This feature is used to handle interrupts from the MC68450 (a 4 channel, 16 bit DMA controller) and the interface's front panel. This document is divided into ten sections, the first being the introduction. The remaining sections detail the interface registers, channel initiation, polling and interrupts, status reporting, front panel interrupts, the configuration routines, the operation control routines, the status reporting routines, and special comments on the MC68450.

At present, grazing incidence mirrors are used almost exclusively as the first optical element in VUV and soft x-ray synchrotron radiation beam lines. The performance of these mirrors is determined by thermal and mechanical stress-induced figure errors as well as by figure errors remaining from the grinding and polishing process. With the advent of VUV and soft x-ray undulators and wigglers has come a new set of thermal stress problems related to both the magnitude and the spatial distribution of power from these devices. In many cases the power load on the entrance slits and gratings in these beamlines is no longer negligible. The dependence of thermally-induced front-end mirror figure errors on various storage ring and insertion device parameters (especially those at the NSLS) and the effects of these figure errors on a class of soft x-ray beam lines are presented. 17 refs., 5 figs., 2 tabs.

Operation of a high speed, triggerable, Video Data Acquisition System (VDAS) including a hardware data compactor and a 16 megabyte First-In-First-Out buffer memory (FIFO) will be discussed. Active target imaging techniques for High Energy Physics are described and preliminary experimental data is reported.. The hardware architecture for the imaging system and experiment will be discussed as well as other applications for the imaging system. Data rates for the compactor is over 30 megabytes/sec and the FIFO has been run at 100 megabytes/sec. The system can be operated at standard video rates or at any rate up to 30 million pixels/second. 7 refs., 3 figs.